The TIP-431 PCI board (see Figure 1) provides multipurpose telecommunications inputs/output support for European CEPT Level 3 and CEPT Level 1 signals. The onboard FPGA can provide additional processing, for example handling of Frame Relay messages.

Each TIP-431 board operates in simplex, i.e. in either an input or an output mode, with software control to switch the direction. In the input mode, either a balanced E-3 can be input via a Twinax connector (J4) or an unbalanced E-1 can be input via a BNC connector (J2). In the output mode, either a balanced E-3 can be output via a Twinax connector (J3), or an unbalanced E-1 can be output via a BNC connector (J1), or a balanced E-3 could be output simultaneous with one of the 16 constituent E-1s. Output frequencies are maintained within the specified line drive and frequency requirements for cable lengths up to 10 m.

Figure 1. TIP-431 PCI Board

The TIP-431 board ships with a driver that can be used with Windows NT 4.0/5.0; a driver for Windows 98 can also be requested. The driver interface includes both control of the board’s operation as well as transfer of data into the board for playback or out from the board for collection. A sample application (with source code) is included that supports E-3 recording to a high-rate SCSI drive or high-rate playback from the same drive (this requires at least a dual Pentium-166 system with a 7200 rpm drive to sustain the full E-3 rate of 4.3 Mbytes/sec without any dropouts).

Figure 2 presents a block diagram of the TIP-431 board. Key to useful operations are the bi-directional FIFO buffers (each direction is 16 Kbytes deep). The interrupt-based software driver transfers data between the on-board FIFOs and a Ring 0 circular buffer using the host computer’s non-paged memory, extending the stored data to 2 Mbytes (470 msec at E-3 rate, and 7.5 sec at E-1 rate). Applications must ensure the capability to consistently fill/empty the circular buffer before it overflows/underflows. Using Windows NT or 98, this becomes the greatest constraint to successful application design, and it is for this reason that the supplied sample E3 disk drive application usually requires dual processors (it will also work with a single processor on a 100 MHz bus).

Figure 2. TIP-431 Board Block Diagram

The onboard FPGA is normally programmed to perform serial-to-parallel conversion for the incoming serial data line, and parallel-to-serial conversion for the outgoing serial data line. The FPGA could also be modified to support extraction of several E1s from an E3 (either the incoming E3 or the outgoing E3), or it could be modified to perform HDLC processing on the serial streams (bit-stuffing on the output, bit de-stuffing/byte alignment on the input). The 87C520 microcontroller is used to send configuration information to the FPGA and to send back FIFO status to the host processor. The FIFO status messages are used to interrupt the host processor; the device driver in the host processor subsequently causes a transfer of 8 KB of data between the TIP-431 board and the Ring 0 circular buffer.

The TIP-431 board is available from stock, with delivery in one to two weeks. Pricing for the TIP-431 board is $2395 for 1..4 units, $2095 for 5..19 units, and $1595 for 20+ units. Two versions of the FPGA currently exist; -A is used to collect and playback complete E3s, -B is used to collect and playback Frame Relay content within the E3s. Other customized versions of the FPGA can be arranged at the time of purchase; contact Pacific Custom Systems for details.

Last modified: 21 August 1999