The T3IO PCI board (see Figure 1) provides T3 telecommunications input / output (I/O) support. Two onboard DSPs permit processing of data just after receiving and just before transmitting. The board supports simultaneous input and output; J1 is an unbalanced BNC input terminated in a 75 ohm transformer load, and J2 is an unbalanced BNC output driven by transformer. The output signal is maintained within the specified line drive and frequency requirements for DS3 signals when using cable lengths up to 300 feet.

Figure 1. T3IO PCI Board

The T3IO board ships with a driver that can be used with Windows NT 4.0/5.0; a driver for Windows 98 can also be requested. The driver interface includes both control of the board’s operation as well as transfer of data into the board or out from the board. A sample application (with source code) is included that supports storing of one DS3 of data to disk or playing back one DS3 of data from disk (note that this application requires a Pentium Windows NT system with a 7200 rpm Ultra-Wide SCSI disk drive).

Figure 2 presents a block diagram of the T3IO board. Key to useful operations is the use of the Input and Output FIFO buffers (each direction is 16 Kbytes deep - optionally up to 128 Kbytes); they permit uneven application processing of the data, which eases development of most applications. The Ring 0 interrupt-based software driver transfers data between the on-board FIFOs and a circular buffer using the host computer’s non-paged memory, extending the stored data space to 8 Mbytes (720 msec for simultaneous collect and playback, 1440 msec for either collect or playback). Successful applications must be able to ensure consistently filling (emptying) the circular buffer before it underflows (overflows).

The T3IO is particularly useful when there is a need to perform preliminary processing on the data, e.g. to access separate packets received using HDLC. The onboard FPGA can be configured to extract HDLC (and byte align), or be configured to just pass the data onward (no special byte alignment). Each onboard TMS320C50 DSP provides 40 MIPS to perform limited processing on all of the data (at T3 rates, this is 5.5 MB/sec of incoming data using the Collect DSP and 5.5 MB/sec of outgoing data using the Play DSP). A typical application of the Collect DSP would be to process HDLC packets (using the hardware to remove fill flags), and adding length indicator information before sending the packet information to the rest of the system. Similarly, the Play DSP could remove the length indicator information before sending the data to the T3 hardware.

Figure 2. T3IO Board Block Diagram

The T3IO is designed to transfer data between other boards (e.g. a DSP board for subsequent packet processing, such as the forthcoming C54CAM board from Pacific Custom Systems, Inc.) using the onboard bus-master DMA controller. When the T3IO board is ready for a transfer, the Collect DSP signals the host computer with an interrupt. The host processor Interrupt Service Routine (ISR) sets up the DMA transfer, and the rest of the transfer to the follow-on processing board is handled by the T3IO board hardware.

Software for the Collect and Play DSPs is uploaded over the PCI bus at system startup. Each DSP application must run from the DSP internal RAM, which is 10 Kwords (20 KB) shared between program and data space. Given the large volume of data at T3 rates (5.5 MB/sec in each direction), most firmware applications will be throughput limited, and will require the benefit of 0-wait-state access only possible with the internal RAM.

The T3IO board is available from stock, with delivery in two weeks. Pricing for the T3IO board is $2395 for 1..4 units, $2095 for 5..19 units, and $1595 for 20+ units. Customized versions of the FPGA can also be arranged at the time of purchase; contact Pacific Custom Systems, Inc. for details.

Last modified: 21 August 1999