Figure 1. C54CAM PCI Board

The C54CAM board ships with a driver that can be used with Windows NT 4.0/2000. The driver interface includes both control of the board’s operation (including loading of the 'C548 firmware) as well as transfer of data into the board or out from the board. Example source code is also provided for both the host computer and the DSP firmware as used to support a PCSI proprietary application that examines Internet e-mail for spam; this is included purely as sample code for how the hardware can be utilized.

Figure 2 presents a block diagram of the C54CAM board. Data comes into the board over the PCI bus via the AMCC bus interface chip, and is sent to a dual port SRAM. This dual port SRAM operates with the DMA FPGA to act as four sets of FIFOs. One pair of "FIFOs" is to used in conjunction with the C54CAM board using the onboard bus-master DMA controller (separate in-bound direction and out-bound direction). A second pair of "FIFOs" utilizes the PCI bus pass-thru mode to act as a target for another board’s DMA controller (both in-bound and out-bound). This supports DMA transfers both to/from other data source boards (such as the T3IO board manufactured by Pacific Custom Systems Inc. for T3 data input/output), as well as transfers to/from the host PC.

When used to process incoming Internet data, a data source board could provide low-level HDLC packets to the C54CAM board. The C54CAM board would then combine the low-level packets into TCP/IP packets, which can then be processed by the DSP. The first CAM set can be preloaded with up to 32,768 desired (or undesired) 32-bit TCP/IP addresses (source address or destination address). The DSP would extract the appropriate TCP/IP address(es) to be sent to the first CAM set to check for a match. Depending on the result, the message could be further processed for keyword matches within the TCP/IP packet data field. The second CAM set can be configured to hold up to 8,192 keywords of up to 10 characters, and the SCORE FPGA provides hardware parsing of words from a message stored in the second dual port RAM. After parsing out and compressing each word, the FPGA submits the word to the second CAM set for match testing, and writes a list of index matches back to the dual port RAM. The keyword searching is implemented in hardware at a rate of about 5 MB/sec, without support from the DSP (which can be doing other simultaneous processing).

Figure 2. Block Diagram of Data Flow within the C54CAM Board

Upon completion of the keyword testing, the DSP can read back a list of index matches and compile a score for the message based on values associated with each keyword. Using a decision threshold, the DSP could then decide whether to forward the message to the host PC for subsequent processing or dissemination. For further processing, the complete TCP/IP message could be loaded into the left-hand dual port SRAM (acting as an out-bound bus-master "FIFO"), the host PC would then be interrupted to notify it that data is available, and the host PC would initiate a DMA transfer using the C54CAM board’s DMA controller. The TCP/IP message would be transferred into a Ring 0 buffer controlled by the Windows NT driver within the host PC, and eventually sent up to a Ring 3 application on the host PC.

On power-up, the boot PROMs on the C54CAM board put the DSP into a loader mode. Firmware for the DSP can then uploaded over the PCI bus based on a hex file generated by the standard Texas Instruments software toolset (either a C compiler or assembler), followed by a command to start firmware execution. Because of the typical tight timing constraints, the DSP application will usually run from the 'C548 internal RAM, which is 32 Kwords (64 KB). There is also 1 MByte of windowed external 3-wait-state RAM (50 reads, 62 nsec writes) for data storage (e.g. session reassembly of multiple TCP/IP streams).

The C54CAM board will be available in December 1999, with subsequent delivery regularly in two weeks. Pricing for the C54CAM board is $3895 for 1..4 units, $3395 for 5..19 units, and $2595 for 20+ units.

Last modified: 5 November 1999